Re: SMP Scheduling

Don Fisher (dfisher@as.arizona.edu)
Tue, 10 Aug 1999 09:04:03 -0700


Horst von Brand,

I am currently building a 4 processor xeon system, each processor
containing 2 megs of L2 cache. I am going to use this for pseudo
realtime image processing. I spent a lot of money for the 2 meg caches
in the hopes that it would keep the main memory from becoming the system
bottleneck.

If the processes are allowed to rotate, I anticipate that each cache
will have to be refreshed. 2 megabytes of data swapped 4 times seems
like a lot of overhead to me. What am I missing?

I hope to have the machine up in a week. If anybody wants to perform
affinity experiments I would be happy to make them an account. Currently
I am still waiting for my heatsinks and memory:-(

thanks
don

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|    Don Fisher				  dfisher@as.arizona.edu  |
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