[ ... ]
> Yours, for example, seems to only be featured of the following 'flushing'
> rules an of no 'ordering' rules at all: (excerpt from the 21172 doc)
>
> - Before a read transaction to an I/O location is processed, all preceding
> write transactions to devices are flushed out of the buffers.
> - Before a read transaction from a PCI device to main memory is
> processed, all preceding write transactions by the PCI device to main
> memory are flushed out the buffer.
>
> The consistency issue is addressed by PCI by ordering rules that applies
> to posted transactions in _both_ directions when a read transaction
> crosses the bridge.
>
> My understanding of the behaviour of the 21172 may be just wrong, but the
> bridge behaviour I quoted above can be easily worked around by drivers by:
>
> 1 - Performing a read (dummy) from the device to memory before raising
> interrupt.
> 2 - performing a read (dummy) from the C code to an IO register from the
> C code before scanning the flags that indicate completion.
I missed to add that only _one_ of the 2 possible reads (dummy read if
necessary) may be needed when ordering rules are applied by bridges.
FYI,
- ncr53c8xx driver is using (2)
- sym53c8xx driver is using (1)
None of them is performing both (1) and (2).
Gérard.
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