On Sat, May 01, 1999 at 06:04:17PM +0100, Paul Jakma wrote:
> On Fri, 30 Apr 1999, Kurt Garloff wrote:
>=20
> On Sat, Apr 24, 1999 at 12:40:15PM +0100, Paul Jakma wrote:
> > the above source file seems to infer that interrupts are always
> > delivered to cpu#0. perhaps this is just for initialisation purposes,
> > i don't know.
> =20
> There's more to do than IRQ handling ...
> Remember the old days of 2.0, where we didn't support the IO-APIC on the
> ix86 to distribute the IRQs. Still, processes could run in parallel ...
> =20
> ah ok, so the kernel only ran on one CPU, but processes could run on
> both. i had thought that this was due to a global kernel lock, not
> interrupts.. by what mechanism can the kernel on cpu#0 schedule a
> task to run on cpu#1?
Not exactly.
Whenever a process makes a system call, it goes into kernel mode, so both
CPUs can be in kernel mode. But with 2.0 only one at a time, because
there was the global kernel lock.=20
2.2 is much more fine-grained. And IRQs are distributed to the CPUs by
supporting the IO-APIC chip.
Note that IRQ13/16 is the IPI (Inter-Processor-Interrupt). One CPU can
send it to the other to signal anything (TLB flush, reschedule). So this
answers your question, does it?
The CPU receiving the timer IRQ will send an IRQ16 to the other to signal
them to reschedule.
> Hopefully widely available K7 SMP systems will accelerate development
> of EV6 SMP and help the 21264 out aswell.
SMP support consists of two parts:
(a) The chipset (routing IRQs and more, ask Ingo Molnar)
(b) The CPU (TLB consistency, ...)
As both K7 and 21264 will probably use the same chipset, it will help (a).
Regards,
--=20
Kurt Garloff <garloff@suse.de>
Linux kernel development
SCSI driver: DC390 (tmscsim/AM53C974)
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