On Sat, Apr 24, 1999 at 12:40:15PM +0100, Paul Jakma wrote:
> the above source file seems to infer that interrupts are always
> delivered to cpu#0. perhaps this is just for initialisation purposes,
> i don't know.
There's more to do than IRQ handling ...
Remember the old days of 2.0, where we didn't support the IO-APIC on the
ix86 to distribute the IRQs. Still, processes could run in parallel ...
ah ok, so the kernel only ran on one CPU, but processes could run on
both. i had thought that this was due to a global kernel lock, not
interrupts.. by what mechanism can the kernel on cpu#0 schedule a
task to run on cpu#1?
Hopefully widely available K7 SMP systems will accelerate development
of EV6 SMP and help the 21264 out aswell.
-- Paul Jakma paul@clubi.ie http://hibernia.clubi.ie PGP5 key: http://www.clubi.ie/jakma/publickey.txt ------------------------------------------- Fortune: /* Halley */(Halley's comment.)
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