Re: 2.2.5 optimizations for web benchmarks?

Linus Torvalds (torvalds@transmeta.com)
30 Apr 1999 15:35:51 GMT

In article <Pine.LNX.3.96.990430083805.2816E-100000@chiara.csoma.elte.hu>,
Ingo Molnar <mingo@chiara.csoma.elte.hu> wrote:
>
>yes and this is a pretty important effect. Also, a TLB miss on a Xeon with
>all the page table info cached takes 3 cycles (and does not cause a
>pipeline stall, so the real cost can be lower than this). So the cost for
>a TLB flush is not all that high as it seems at first sight.

Note that this is certainly new to the newer intel CPU's.

Older intel CPU's not only killed the pipe on a TLB miss, they also did
all TLB handling uncached - so that a regular TLB miss cost was
basically the cost of (twice) bringing something in from the L2.

If they indeed do it in three cycles without a stall, that's a
surprisingly _huge_ improvement for them. Good show.

Linus

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