> Its Non-Maskable-Interrupt. Its an interrupt line on a PC that is normally
> wired to the parity error signals off the memory, but on some PC's used
> for power management.
For the "wishlist" category, in case someone is looking for a kernel
project: the intel chipsets (and probably many others) report where
parity errors occur. They'll indicate not only that an error occured
(thus disambiguating the NMI) but also which slot it occured in.
They will report correctable errors (1-bit) as well -- so you could get
notice that a simm is failing before it actually fails.
One-bit errors should be corrected before they become two-bit errors.
Unfortunately error detection only occurs on read -- and with some
chipsets, error correction only occurs on write (some chipsets have an
auto-writeback mode to correct errors). A natural idea is to have a
daemon that walks through physical memory at a slow rate, detecting and
correcting 1-bit errors.
chipset docs are available in pdf off intel's website. Requires some
digging.
Dean
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