Take a look at the book "in search of clusters" it goes into a lot of
detail on everything that is needed to run parallel systems, both SMP and
cluster setups. It boils down to the fact that you can get better
performance from the existing types of chips then you could get from
creating an on-chip SMP.
David Lang
On Thu, 15 Apr 1999 bwoodard@cisco.com wrote:
...
>
> > > 2) Why don't CPU designers revisit the RISC revolution and make much
> > > simpler processors with shallower (simpler) pipelines and then pack
> > > two or four processors on one die creating one chip that would appear
> > > to the kernel as a four processors. Then let you kernel developers
> > > play with locking and the application software developers multithread
> > > their code to take advantage of it. It seems to me like it moves the
> > > problem of speed optimzation into software where it is much easier to
> > > profile and tweak. It could be that many of the fancy tweaks built
> > > into microprocessors today might not be getting used all that often
> > > because of lagging compiler technology or because the designer thought
> > > something was important when in fact it is rarely used in modern
> > > code. How do we know that the Pentium II or III is not just chocked
> > > full of bloat etched into silicon?
> >
> > The ix86 insn set is hard to support with a simple design. Actually, what
> > K6, PII and PIII do is to translate those insns in internal RISC like insns
> > which can be nicely handled by the execution units.
> >
> > If you want to get rid of that much silicone, you have to dwitch
> > architecture and use PPC, ARM, Alpha or whatever ...
> >
> > On the other hand, the x86 code is very dense, resulting in relatively short
> > executables.
> >
>
> One more question then. Since ix86 instruction set is so easy to
> support what takes up all the die space?
>
> Also I still don't understand why chip designers don't design simpler
> chips that behave like multiple processors rather than going to all
> the work of having deep pipelines and all the complexity associated
> with that e.g. speculative execution, out of order execution...
> i.e. Is there some reason they don't make a chip which is essentially
> four 486's, cache and all the glue circuitry needed to make them
> capable of running SMP.
>
> -ben
>
> -
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