On Tue, Apr 13, 1999 at 08:15:55PM -0700, bwoodard@cisco.com wrote:
> This long thread about the evils of winmodems has made me wonder about=20
> two things.
>=20
> 1) Why shouldn't hardware engineers make cheap peripherals which
> require significant CPU assist and then just have an extra CPU around
> to ensure that the user experience is responsive while one CPU is
> doing things like the modem or sound processing. It seems to me that a
> cheap SMP box would be much more useful than a computer with a whole
> bunch of seldom used specialized chips in it. I'd love to have my
> kernel compiles double in speed just by shutting down my modem or
> sound card.
There is a number of things hwhich you can do with really cheap specialized
hardware (say a few thousand transistors) which would require a significant
load on an expensive general purpose chip (millions of transistors on the
current CPUs). So, it's no good deal.
Think about sound chips, modems, VGA, Serial, network chips and the like. I
don't want my CPU load go up to 0.5 because of transporting data other the
net.
> This brings me to my second question about SMP:
>=20
> 2) Why don't CPU designers revisit the RISC revolution and make much
> simpler processors with shallower (simpler) pipelines and then pack
> two or four processors on one die creating one chip that would appear
> to the kernel as a four processors. Then let you kernel developers
> play with locking and the application software developers multithread
> their code to take advantage of it. It seems to me like it moves the
> problem of speed optimzation into software where it is much easier to
> profile and tweak. It could be that many of the fancy tweaks built
> into microprocessors today might not be getting used all that often
> because of lagging compiler technology or because the designer thought
> something was important when in fact it is rarely used in modern
> code. How do we know that the Pentium II or III is not just chocked
> full of bloat etched into silicon?
The ix86 insn set is hard to support with a simple design. Actually, what
K6, PII and PIII do is to translate those insns in internal RISC like insns
which can be nicely handled by the execution units.
If you want to get rid of that much silicone, you have to dwitch
architecture and use PPC, ARM, Alpha or whatever ...
On the other hand, the x86 code is very dense, resulting in relatively short
executables.
Regards,
--=20
Dipl.Phys. Kurt Garloff <kurt@garloff.de> [Wuppertal, FRG]
Plasma physics, high perf. computing [Linux-ix86,-axp, DUX]
PGP key: see mailheader / key servers [Linux SCSI driver: DC390]
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