Questions about MMU design for PA-RISC
Paul J.Y. Lahaie (pjlahaie@ottawa.com)
Wed, 10 Mar 1999 22:04:36 -0500
I'm currently in the process of trying to get some PA-RISC MMU code
into the kernel and due to some odd restrictions on the PA-RISC TLB
handling, I'm looking for some advice on getting something working.
Basically the PA-RISC has a software TLB (w/ possible hardware assist in
some implementations, but I will be concentrating on software TLB
handling for now) and one of the restrictions is that the TLB miss
handler cannot fault on a TLB miss. I've looked at the Mach PA-RISC
code and they seem to handle TLB misses by doing an equivalent mapping
of the physical RAM and putting the kernel at the beginning. Can this
be done with the Linux MMU code? If not, how do I map in the pte
structures and make sure I don't TLB miss on them? Should I just
explicitly map any PTE table before I access it? I've been going
through the PA-RISC book, Linux MMU code (mostly the x86 stuff) and the
Mach PA-RISC code. Is there something else I should be reading?
- Paul
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