L2 cache sizes different: BIOS bug?

Richard Gooch (rgooch@atnf.csiro.au)
Wed, 3 Feb 1999 23:28:04 +1100

Hi, all. I've just discovered, to my horror, that a dual PII machine
here has different L2 cache sizes for each CPU. The boot CPU (#1) is
reported to have 0 kB whereas the other CPU (#0) is reported to have
512 kB (as expected for a PII). This is with 2.1.126. I get the same
with 2.2.0.

I don't think it's just a matter of a bug in the contents of
boot_cpu_data.x86_cache_size (this was my first suspicion),
however. Running a memory benchmark test suggests that there is indeed
one processor without an L2 cache.

The system is a Digital PC 5000 (the BIOS reports it as PC 5500
266). The CPUs are 333 MHz. I've checked the BIOS settings and cache
is enabled. It doesn't distinguish the CPUs.

Has anyone else experienced a similar problem? Is there a known
workaround? Is this a BIOS/configuration bug or is somehow the L2
cache on the boot processor not working?

% cat /proc/cpuinfo
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 3
model name : Pentium II (Klamath)
stepping : 3
cache size : 512 KB
fdiv_bug : no
hlt_bug : no
sep_bug : no
f00f_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 2
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov mmx
bogomips : 265.42

processor : 1
vendor_id : GenuineIntel
cpu family : 6
model : 3
model name : Pentium II (Klamath)
stepping : 3
cache size : 0 KB
fdiv_bug : no
hlt_bug : no
sep_bug : no
f00f_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 2
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov mmx
bogomips : 264.60

Regards,

Richard....

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