/*
* Careful with this one. We do not use 'true' logical
* delivery, as we set local APICs to LDR == 0. But
* 0xff logical destination is special (broadcast).
* Any other combination will cause problems.
*/
#if 0
entry.dest.logical.logical_dest = 0xff;
#else
entry.dest.logical.logical_dest = 0x00;
#endif
if (entry.dest.logical.logical_dest = 0xff;)
{
cat interrupts
CPU0 CPU1
0: 13748 27 XT-PIC timer
1: 101 128 IO-APIC-edge keyboard
2: 0 0 XT-PIC cascade
}
if (entry.dest.logical.logical_dest = 0x00;)
{
cat interrupts
CPU0 CPU1
0: 73540 0 XT-PIC timer
1: 1996 1868 IO-APIC-edge keyboard
2: 0 0 XT-PIC cascade
}
These boards have a broken apic-timer.
I get random 'spurious APIC interrupt, ayiee, should never happen.'
when the timer on the second CPU is anything but 0. Note history
is repeated everytime CPU1's XT-PIC timer is not "zero".
I will agree that this is a hammer method to success; however, why should
we every have a XT-PIC interrupt register on anything other than CPU0?
Cheers,
Andre Hedrick
The (NEW) Linux IDE guy
The APC UPS Specialist for Linux
http://www.dyer.vanderbilt.edu/server/udma/
http://www.dyer.vanderbilt.edu/server/apcupsd/apcupsd-3.5.2.bin.tar.gz
You just need a bigger hammer, or learn how to swing the one you have better.
(C) me.....
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