Re: Structure vs purism ?

Matti Aarnio (matti.aarnio@sonera.fi)
Mon, 25 Jan 1999 03:04:33 +0200 (EET)

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Ralf <ralf@uni-koblenz.de> wrote:
> On Fri, Jan 22, 1999 at 04:02:20PM -0500, Richard B. Johnson wrote:
> > If you get RAM that runs at twice cache-speed you won't need a cache
> > (there will probably always be an instruction cache so branch prediction
> > works).
>
> MP systems are getting more and more popular. For them the requirement for
> caches will continue to exist. Even Cray started to using instruction
> caches for the SV vectors; good 'ole Seymour would probably commit suicide
> if he'd know that ;-) Large efforts in CPU and bus systems over the last
> years has gone into technique which allows to tolerate latencies.
...
> .... The actual hope is that these techniques combined with faster
> RAM technologies of the future will provide a short enough latency to
> allow CPUs to keep busy most of the time.

Today I spent a few hours browing RAMBUS pages and presentations
about this issue. Reading the thing about interleaved pipelined
memory subsystems brought me some memories from elsewere, and
true enough, DEC 7000 and 10000 systems had similarly behaving
large-scale bus in them. (They were introduced in 1992, which
means the designs and patents are at least couple years older..)
Similar designs can be found from CRAY supercomputers too, I think.

The idea is that to access some memory item one sends the requests
out, and waits the given response time -- 80 ns or so, however
there can be multiple outstanding requests issued to the memory
subsystem as each requests occupies only 20 nanoseconds.