Yep, and while CISC machines have these elegant LOCK+INCmem instructions,
RISC systems tend to have: MEM->REG loads, REG->REG operations, REG->MEM
stores. Specifically, they do *not* have MEM->MEM operations!
In case of Alpha, the code is:
1: ldl_l tempreg,memaddrreg ; Load Long Locked
addl tempreg,valuereg,tempreg ; Add to loaded value
stl_c tempreg,memaddrreg ; Store Long CondLock
; This is the real jevel at Alpha, hardware
; assists multi-processor coherence by monitoring
; previous "load defined" lock address events
; in the external bus. If a write happens
; at the given address, then 'tempreg' will
; be cleared at the store time.
; (I should pick an Alpha Architecture Manual
; and recheck my memory, "obviously" it should
; set the reg to be non-zero when the store
; succeeds.)
beq tempreg,2f ; ... thus allowing this somewhat
; convoluted way to branch back to label 1
; in case the memory atomicity was violated
; during the store.
.section .text2,"ax"
2: br 1b
.previous
> Alan
/Matti Aarnio <matti.aarnio@sonera.fi>
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