I checked. As far as I can tell, PCI 2.1 does not say that configuration
reads must not have side-effects. The standard configuration registers
are defined to not have read side-effects, and not-implemented registers
are defined to not have side-effects. As far as I can tell, if a device
provides a meaning for a specific register in the device-dependent part
of the configuration space, it *may* define it to have side-effects.
(This is a profoundly ugly thing to do, but that is another issue.)
However, the device must support in a sensible way any combination of
byte-enables is a DWORD configuration access, and must also support
linear bursting. Therefore, controlling those side effects may be
impossible.
I can't find any place where configuration space must be prefetchable.
So, I started out trying to prove Martin right, I find myself agreeing
that devices that have read side-effects in configuration space are
certainly very broken, but may still be PCI 2.1 compliant. Prove me wrong.
-- Steve Williams "The woods are lovely, dark and deep. steve@icarus.com But I have promises to keep, steve@picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."
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