> 1 - Read the Interrupt Status Register (ISTAT)
> If completion interrupt (INTFLY)
> 2 - Write the ISTAT to clear the interrupt condition.
> 3 - Reread the ISTAT. This read will ensure that PCI posted writes
> that may have occured between (1) and (2) are flushed and that the
> Interrupt condition is actually cleared.
> (This seems overcommitting, but hopefully it is not)
> 4 - Scan the completion queue.
>
> Between (1) and (2) the controller may have written to memory some
> completion data and these transactions may be posted.
> The write to the ISTAT (2) may also be posted.
> (3) ensures that all this stuff will be actually visible by the
> corresponding parts at the moment the completion queue is scanned
> by the C code.
just out of curiousity, does the problem remain if the NCR driver is
booted in non-ioremapped mode? in/out is slower but much more conservative
and this should exclude lots of cache invalidation/chipset posted write
bug possibilities.
-- mingo
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