I'm really surprised about why so many BIOSes will mark interrupts
edge-triggered. I don't know why they do it, as it's almost always safe
_not_ to do it (the only device that it's not safe for that I know of is
the timer - I'm sure there are others, but they must be rather rare).
Does anybody on the kernel list know how the BIOS makes its decisions
about how to mark interrupts edge vs level-triggered? It would be
informative to know, because maybe we should override it (but without
knowing what the BIOS does I feel very nervous indeed about overriding
it).
> This is probably dumb but how is the choice made between edge triggered
> and level triggered interrupts? I don't recall seeing a bios setting.
The BIOS essentially tells us which to use by virtue of the MP table.
There's a feature there saying what kind of interrupt we should use. For
example, for ISA devices we should use edge-triggered not because that's
the right thing to do, but because that's the historcially correct thing
to do - and we have no way of knowing whether the device requires us to do
it or not.
To some degree edge-triggering is "safer", because at least you don't end
up taking endless interrupts. At the same time it's certainly not safer as
a reliability issue, because you can much more easily have lost
interrupts.
See the function "irq_trigger()" in arch/i386/kernel/io_apic.c, or more
exactly the "MPBIOS_trigger()" thing that parses the BIOS MP table to
determine whether to use edge (0) or level (1) triggered interrupts.
> is it a kernel flag that I can pass to the APIC code? I started having
> this problem after I put in an SIIG ISA card consisting of a prom that
> would supposedly allow me to use an LS-120 - it made all kinds of goofy
> changes to the system bios settings and even though I cleared CMOS, the
> mother board has not been working in SMP mode with any heavy IO.
You could try to make irq_trigger() always return 1 for PCI devices,
regardless of what the MP table says.
Linus
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