On Wed, Sep 09, 1998 at 12:54:26PM +1200, Chris Wedgwood wrote:
> Can't be done. Its been looked at, and for a fully feature networking
> stack, its much harder than this.
Yeah, I know. It's something I'm working on :-) Well ok, I may skip
fully featured. But I intend to get a VNC client over single threaded
TCP over ethernet running on an FPGA before the end of the year.
> Look at what cisco have, its pretty much bleeding edge, and its
> nowhere near this flash. Implementing a sull network stack or even
> fib in silicon I fear is far from trivial.
A _full_ network stack is far from trivial in C, let alone any hardware
languages. A rough hack is more plausible, and my FPGA tools are pretty
good.
By "fast path", I meant matching packets for routing and direct
switching, perhaps ICMP responses. Everything more complex is dumped to
external RAM to be processed by a CPU. But even that can be helped by
chopping up packets cleverly, doing checksums as you go, having the FPGA
direct CPU context switches etc. (This would be for a general network
stack; the TCP client I mentioned really is optimistically planned for a
standalone FPGA).
> It sounds to me like you don't want an FPGA in/on the CPU - you want
> a FPGA device on a PCI hard with some other fancy stuff. These are
> available, with PPC (604?) host processors and 8MB on the card too.
Got several, thanks. With various network interfaces stuck on. I built
the 10Mbs ethernet connection with a soldering iron, lots of wire and
various components a couple of weeks ago, I am feeling very proud of
it. I shall add some flashing lights soon, that will make it impressive ;-)
> Again, I doublt you'll get GB ethernet going on an FPGA. GB ethernet
> done properly is already pushing the spectrum of what cost a
> effective dedicate ASIC can do, let alone the added complexity and
> overhead and an FPGA.
Gig ethernet is 32 bits every cycle at 33MHz. A fast Altera FPGA can
_just about_ handle that kind of data and process it (FIFOs,
packetising, priority queuing. Nothing posh -- you can write it, but
the circuit will run too slowly if it fits at all). You still need an
ASIC to talk to the wire.
Sending data that fast out to RAM while reading it back at the same time
while giving another processor access to the RAM... Now that is too
much, for now. Too much routing, too many independent RAM ports.
I could be wrong. I hope not, I have to work on this stuff soon enough :-)
> Not to mention, modern CPUs are complex beats - you can't just tack
> on functional units and expecting evetything to work.
I know, I have tried to copy a modern CPU in an FPGA ;-)
I gave up when I realised the _design_ was taking forever.
Copying a really simple, old-fashioned CPU. Now that's a lot easier!
Giving away what I do...
-- Jamie
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