> hm, nope. Even on the PII i can barely make it a win. The problem is that
> to generate IP checksums we have to do addition with carry - on the MMX
> engine which has no carry, no flags and no branch instructions and no
> effective ways of mixing integer and MMX instructions. Thus my code is
> quite tricky and it saturates the PII completely so i'm not surprised at
> all that it does not play well on a P5.
I looked at this back when the MMX extensions were announced and there
seemed to be a way to do it. IIRC, there's an instruction which will
extend a register full of n-bit values into 2 registers full of 2n-bit
values - sort of like sign extend. This lets you do all your math in 16
bit so carry or branch logic is no longer an issue. So you use one MMX
register as 4 16-bit accumulators, one as a load target for 8 8-bit
values, and two as buffers for zero extending those values. Then
processing 8 characters can be (no idea what the opcodes are anymore)
load *p to a (1 cycle)
extend a to b and c (I think this is two 1 cycle instructions)
add b to d (1 cycle)
add c to d (1 cycle)
increment p (1 cycle)
...which results in four partial results in d which can be merged at the
end of the loop into the final checksum.
I posted something like this to linux-kernel about two years ago, I think.
Would be interested to see your current version of the code.
-- "Love the dolphins," she advised him. "Write by W.A.S.T.E.."
- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.rutgers.edu Please read the FAQ at http://www.tux.org/lkml/faq.html