FreeHDL <http://www.freehdl.seul.org/>
Not much visible progress, though.
I'm also quietly doing a Verilog compiler that will cope with behavioral
and structural models, but it's too early to share. When I parse and elaborate
a reasonable portion of the language, and settle the internal interfaces,
I'll be ready to open up.
There is, as you pointed out, sparse little available support for synthesis
of FPGA devices. If someone can figure out the structure of the bitstream
that goes to Xilinx FPGAs, I'd love a pointer.
-- Steve Williams "The woods are lovely, dark and deep. steve@icarus.com But I have promises to keep, steve@picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."
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