On Thu, 03 Sep 1998, Andre M. Hedrick wrote:
....
>Andrew and Michel,
>
>Is our patch valid only for VP3 and not for VP1/VP2?
No, basically it works fine with all VIA chipsets, because VIA has (wisely)
kept the same IDE controller structure across chipset revisions. The
Southbridge chip is basically unchanged.
I guess we'll only need some small changes for the new ATA-66 capable
VIA Southbridge chip. ;-)
>
>Second, I have discovered the hardware that ide interfaces go only
>as fast as the slowest device. There may be a timing error due to
>device or conflicts or something of this nature.
>
>What do you say?
How do you mean? Do you mean the interfaces (ide0 & ide1) or the drives (hda &
hdb, or hdc& hdd)? I am pretty sure the code detects each drive individually, so
for each drive one gets the ideal timing.
To demonstrate this: Hans, can you edit your patched triton.c, and define
DISPLAY_APOLLO_TIMINGS? Then please recompile, and report the output from
/proc/via.
This will give us a very detailed report of each drive timing parameters.
>This may be a case of individual device tuning of the chipset.
Let's see the output from Hans' /proc/via. This should clear all doubts.
Cheers,
-- Andrew D. Balsa andrebalsa@altern.org
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