OK, so here's a question: part of interrupt latency should include at
least a couple of register reads across the PCI bus. I'm not much of
a PC driver person, so I'm not sure that what I'm saying make sense,
but every driver I've ever worked on was basically:
take the interrupt
read some state across the bus
do something, usually a DMA
write some state across the bus
clear the interrupt
with the ordering being changed depending on how smart/dumb the driver is.
Anyway, the deal is that reading/writing state across the bus is like
an uncached memory access and used to take around a usec or so. If,
and this shows how little I know, the read/write is 10% or so of a null
interrupt, then I'd like to include that cost. Any ideas?
Also, is anyone out there interested in making this benchmark exist? I
really want to know what these numbers are...
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