> Date: Fri, 19 Jun 1998 14:26:51 +0200
> From: Erik Corry <erik@arbat.com>
>
> In article <19980619162224.C118@caffeine.ix.net.nz> you wrote:
> > On Thu, Jun 18, 1998 at 09:00:46PM -0700, David S. Miller wrote:
> >> Not totally true, as Ingo has shown doing IP checksums on MMX was not
> >> significantly different in complexity from doing it on Sparc VIS.
>
> Doesn't give much benefit, though, according to Mingo
> http://x2.dejanews.com/getdoc.xp?AN=362293483
>
> "but for most RL MTU's the FPU save/restore operation eats
> a considerable amount of the saved cycles"
>
> Sore point, because this initially was our problem on sparc64 VIS, and
> this gap closed up once we implemented smart FPU saving throughout the
> sparc64 port. Now it's a non-issue and the FPU isn't save in most
> cases even under high interrupt and overall load.
As Adam Richter pointed out a few weeks ago the x86 smart FPU saving code
is more or less ineffective on glibc systems, because all glibc programs
initialise the FPU in the startup code. For full benefits of very smart
FPU state saving glibc needs to be fixed first (assuming the CPU spends
more time in usermode than in kernelmode)
I guess the sparc64 glibc doesn't have this problem?
-Andi
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