In the case of 8259:
a) A call to disable_irq will increment the disabled_irq[irq_nr] counter
and will hard mask the irq.
b) A call to enable_irq will decrement the disabled_irq[irq_nr] counter
and will hard unmask the irq.
This takes into account multiple calls to disable and enable by
hard enabling the irq whenever the first enable_irq is called.
In the case of io_apic:
a) A call to disable_irq will increment the disabled_irq[irq_nr] counter
b) A call to enable_irq will decrement the counter and olny when the
counter gets to zero does the software emulate all the pending interrupts.
The logic seems different when compared to the 8259
Take this scenario
8259A CASE:
TIME CPU0 CPU1
1:disable_irq
2: disable_irq
3:enable_irq
**** AT THIS POINT IRQ IS ENABLED AND THE HARDWARE UNPENDS ALL THE PENDING
INTERRUPTS
4: enable_irq (decrements the counter and does
nothing else)
IOAPIC CASE:
TIME CPU0 CPU1
1:disable_irq
2: disable_irq
3:enable_irq (decrements the counter but nothing else happens)
4: enable_irq ( ALl the interrupts are unpended by
enable_irq)
Only at Time 4 units does the interrupts get unpended( by the software),
while for 8259a at Time 3 units interrupts get unpended (by the hardware).
Is there something we are missing here, does 8259a controller work
differently?
Thanks in advance for your input
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