Re: Triton DMA

Gerard Roudier (groudier@club-internet.fr)
Sat, 29 Nov 1997 11:00:12 +0100 (MET)


On Sat, 29 Nov 1997, Rogier Wolff wrote:

> mlord wrote:
> >
> > Gerard Roudier wrote:
> > >
> > > On Thu, 27 Nov 1997, mlord wrote:
> > >
> > > > DMA transactions are *exactly* the same speed/timing as PIO transactions
> > > > (thanks to the same cycle time of 120ns, plus pipelining/prefetch in the
> > > > chipsets for the PIO transfers). Except for Ultra33 DMA, which *does*
> > > > include 32-bit CRC checking (far superior to parity).
> > >
> > > Could the Linux IDE guy explain to a Linux SCSI guy who does
> > > not want to die in ignorance, in which this 32-bit CRC is so
> > > superior to parity ? ;-)
> >
> > A single parity bit will only detect odd numbers of bit errors
> > (1-bit errors, 3-bit errors, ...), not even numbers.
> >
> > A 32-bit CRC will detect both even and odd numbers of bit errors.
>
> In the beginning, parity was considered reasonable: Measurements
> showed that say only one in a million bits went wrong. In that
> situation, using parity is not that bad: there is just a 1 chance in a
> million that a second bit error occurs in that same byte. You
> possibly miss just one error in a million, 999,999 are flagged
> correctly. This means that 1 in 1.25e11 bytes is incorrectly flagged
> as correct while in reality it is wrong.
>
> However nowadays we know, that it doesn't always work like that. You
> might have a 1 in four million chance of a BYTE going wrong, with an
> average of 4 bits wrong in that byte (i.e. the byte is completely
> random). Still just one bit in a million is wrong, but a completely
> random byte has a 50/50 chance of getting the right parity by
> accident. So now you're getting 1 byte in 1e6 bytes flagged
> as correct while in reality it is wrong.
>
> In the first case, you get one error per day of full-time copying. In
> the second case you get 5 errors per second. (Assuming 5Mb per
> second).

Thanks for the explanation.
Btw, I did not observe that my Ultra Wide SCSI BUS ever got 40 undetected
errors per second. But I read that IDE DMA may corrupt data and noticed
that PIO is often recommended against DMA.
My opinion about IDE BUS is that it is not a suitable IO bus for mass
storage devices, but looks like some extension of some system bus, since
it is neither terminated, nor uses differential signals.
If I enjoyed driving trabants with race car engine, I would probably
use IDE Ultra 33 devices.

Gerard.