> Gerard Roudier wrote:
> >
> > On Thu, 27 Nov 1997, mlord wrote:
> >
> > > DMA transactions are *exactly* the same speed/timing as PIO transactions
> > > (thanks to the same cycle time of 120ns, plus pipelining/prefetch in the
> > > chipsets for the PIO transfers). Except for Ultra33 DMA, which *does*
> > > include 32-bit CRC checking (far superior to parity).
> >
> > Could the Linux IDE guy explain to a Linux SCSI guy who does
> > not want to die in ignorance, in which this 32-bit CRC is so
> > superior to parity ? ;-)
>
> A single parity bit will only detect odd numbers of bit errors
> (1-bit errors, 3-bit errors, ...), not even numbers.
>
> A 32-bit CRC will detect both even and odd numbers of bit errors.
I still donnot have doc about Ultra DMA, however, general considerations
could be:
- A single parity error only misses even bit errors that happens on a data
line (1 byte for SCSI).
- Single parity is easy to implement by simple hardware. and thus very
_fast_.
- A CRC per data block misses _bunches_ of multiples errors.
- Computing the CRC is a not negligible _overhead_, especially if you have
to do this by software.
Gerard.