Re: New Small Cyrix patch

Pierre Mai (
18 Nov 1997 15:03:15 +0100

>> This patch will: 1) Correctly reset the 6x86(L) SLOP flag so
>> that bogomips are correctly calculated on boot (on 6x86 CPUs,
>> bogomips should _always_ be reported as the core clock rate +/-
>> 1 MHz).

LD> This is chipset dependant. As I reported previously, VXtwo and
LD> VXpro+ motherboards report totally different bogomips. The
LD> VXtwo will report the bus clocking, sans multiplier, within
LD> 20MHz. The VXpro+ will report it to 20MHz within bus clocking,
LD> with multiplier. Both have the UMC8886/UMC8887 combo, which
LD> incorrectly reports in /proc/pci, as shown below.

Hmmm, isn't the UMC8886 a _486_ PCI Chipset? At least I have it in my
Biostar MB, which most definitely is 486-only (running AMD 5x86-P75
which is the 486DX4WB with 133MHz internal clock, 33MHz external):

processor : 0
cpu : 486
model : Am5x86-WB
vendor_id : AuthenticAMD
stepping : 4
fdiv_bug : no
hlt_bug : no
fpu : yes
fpu_exception : yes
cpuid : yes
wp : yes
flags : fpu
bogomips : 66.56

PCI devices found:
Bus 0, device 18, function 1:
IDE interface: UMC UM8886BF (rev 16).
Fast devsel. IRQ 14. Master Capable. No bursts.
I/O at 0x0.
I/O at 0x0.
I/O at 0x0.
I/O at 0x0.
I/O at 0x3000.
Bus 0, device 18, function 0:
ISA bridge: UMC UM8886A (rev 14).
Medium devsel. Master Capable. No bursts.
Bus 0, device 16, function 0:
Host bridge: UMC UM8881F (rev 4).
Medium devsel. Master Capable. No bursts.
Bus 0, device 5, function 0:
Non-VGA device: NCR 53c810 (rev 1).
Medium devsel. IRQ 9. Master Capable. Latency=64.
I/O at 0x6000.
Non-prefetchable 32 bit memory at 0xf4001000.
Bus 0, device 4, function 0:
VGA compatible controller: S3 Inc. ViRGE (rev 6).
Medium devsel. IRQ 255. Master Capable. Latency=32. Min Gnt=4.Max Lat=255.
Non-prefetchable 32 bit memory at 0xf0000000.
Bus 0, device 3, function 0:
Multimedia video controller: Unknown vendor Unknown device (rev 18).
Vendor id=109e. Device id=350.
Medium devsel. Fast back-to-back capable. IRQ 12. Master Capable. Latency=32. Min Gnt=16.Max Lat=40.
Prefetchable 32 bit memory at 0xf4000000.

Hmmm, so it seems that the UMC8887 would be the 6x86 Host-Bridge,
whereas they kept the UMC8886 as IDE/ISA-Bridge... But this must be
another revision or something, because at least the UMC8886 should
identify correctly...

LD> And, as I said, this is a UMC board, not VIA. there is no VIA
LD> hardware on it whatsoever. i'm not sure if this is caused by
LD> overlapping id's, or just a typo in pci.h/pci.c. One of these
LD> days I will get around to fixing it. :)

Regs, Pierre.