Re: question about M2 "feature" (fwd)

Patrick St. Jean (
Thu, 24 Jul 1997 08:36:18 -0500 (CDT)

It looks like this one didn't show up for some reason (at least I didn't
get it...), so here it goes again!

--- repost ---

Ok... here's the dirt straight out of Cyrix's databook:

Page 1-1:
To provide for multimedia operations, the cache can be turned into a
scratchpad RAM memory on a line by line basis. The cache area set aside
as scratchpad memory acts as a private memory area for the CPU and does
not participate in cache operations.

Page 1-16:
The 6x86MX CPU has the capability to "lock down" lines in the L1 cache
on a line by line basis. Locked down lines are treated as private memory
for use by the CPU. Locked down memory does not participate in hardware
cache coherency protocols. Cache locking is controlled through the use of
the RDMSR and WRMSR instructions.

Page 2-61 (too long... I'm not typing this one...)

Here's the URL to get the databooks:

Hope this helps...


| Patrick St. Jean                                 |
| Programmer & Systems Administrator                     +1 713-977-4177 x106 |
| Larson Software Technology                |