About ioremap() and L2-Cache

Para Group (para@sun670.sebuaa.ac.cn)
Tue, 22 Jul 1997 22:29:46 +0900

Hi, every one
I read the ioremap source of Linux-2.1.x and find the kernel doesn't care
about the Pentium new bit setting PWT ( page cache write through ) and PCD
( page cache disable ), only PCD is defined but never used in the kernel source.
We also read the FreeBSD 2.1.5 kernel source. In that source code, the
pmap_mapdev() setup the page table entry with the PCD and PWT bits set. In
Linux2.1.x, I can not find the bit set, if the L1-Cache or L2-Cache cache the
I/O address space memory, how the device driver communicates with the device.
I also write a pseudo device driver in Solaris2.x, Solaris2.x DDI/DKI provide
the device access attributes which can inform kernel whether the I/O space
address memory can be cached or not. The default attribute is without cache
enabled. But I wonder why when I disable L2-Cache from BIOS settings there is
still a slowing down of my test program. Who can tell me how the BIOS do with
L2-Cache and the principle of PC main-board.

thank a lot

Michael L.
07/21/97