TritonII IDE interface not PCI compliant?

Rogier Wolff (
Mon, 16 Jun 1997 17:15:31 +0200 (MET DST)


Has anybody here seen anything like the following?

If my preliminary tests are correct, the IDE interface from the
Triton/Natoma chipset, the 82371SB chip, is not using the "Latency"

I have a board in my computer that requires about 6Mb per second
throughput on the PCI bus. That's not nearly enough to saturate
the bus right? Anyway, that board has a buffer for 128 bytes.
That is enough for 20 microseconds of data, but it will only request
the bus when the buffer is about half full. Thus, it needs the bus
within a span of 10 microseconds. If my calculations are correct,
a latency of 32 cycles means about one microsecond.

With two or three devices active on the bus I'd expect a max latency
around a few microseconds. However my board reports that it gets
locked out for long enough (10 us) that it gets a buffer overrun.

This is my IDE interface according to /proc/pci:

Bus 0, device 1, function 1:
IDE interface: Intel 82371SB Natoma/Triton II PIIX3 (rev 0).
Medium devsel. Fast back-to-back capable. Master Capable.
Latency=32. I/O at 0xe800.

Whenever I do disk access (dd if=/dev/hda of=/dev/null works nicely),
I get tons of overruns from the other board.

To me this indicates that the 82371SB isn't honoring the latency
counter. Anybody have a different explanation? Anybody see the same?


Roger Wolff.