Re: ISA bus and SLOW_DOWN_IO

Alan Modra (alan@spri.levels.unisa.edu.au)
Sun, 25 May 1997 19:48:53 +0930 (CST)


"Richard B. Johnson" <root@analogic.com> said:
> In the following session, MS-DOS debug is used to read and write
> using the port at 0x80. Note that what is written, will be read back.
> Therefore, it is NOT an "unused" port. Further, everything written to
> any port address of 0xffff and below will appear on the ISA bus.
> Unfortunately, due to poor design, most boards do not decode all
> the address bits. This means that you could access a board without
> intending to do so. I don't have the IBM "bible" here, but I believe
Not by writing to 0x80

> that the port at 0x80 is the first DMA page register. If so, it
Yes

> is hardly an "unused" port. The early IBM design used DMA Channel 0
> to do dummy DMA cycles for RAM refresh, therefore this port may
> be available for use but....
The first DMA page register doesn't correspond to DMA channel 0. 0x87
is the page register for channel 0 (and 0x8F for refresh) Here's the
complete mapping, courtesy of Ralf Brown's interrupt list (inter53*
from your neighbourhood ftp site)

PORT 0080-008F - DMA PAGE REGISTERS (74612)

0080 RW extra page register (temporary storage)
0081 RW DMA channel 2 address byte 2
0082 RW DMA channel 3 address byte 2
0083 RW DMA channel 1 address byte 2
0084 RW extra page register
0085 RW extra page register
0086 RW extra page register
0087 RW DMA channel 0 address byte 2
0088 RW extra page register
0089 RW DMA channel 6 address byte 2
008A RW DMA channel 7 address byte 2
008B RW DMA channel 5 address byte 2
008C RW extra page register
008D RW extra page register
008E RW extra page register
008F RW DMA refresh page register

The original IBM bios used writes to 0x80 to help debug bios progress
during bootup (Manufacturing Diagnostics port). As such, writing to
IO port 0x80 is a very good way to reduce the frequency of IO accesses
to a slow IO card.

>[more deleted misinformation]
> I suggest that the macro be changed to:
>
> pusha
> popa

A poor choice. Do your sums. Consider modern processor clock speed
and caching. Then realise that the ISA bus is likely to be behind a
PCI bridge with posted writes.