> The ncr driver compiled as a module, is not loaded because of a symbol not
> exported by the kernel:
> /lib/modules/2.1.37/scsi/ncr53c8xx.o: unresolved symbol x86
> I think we should add:
> EXPORT_SYMBOL(x86);
> in
> arch/i386/kernel/i386_ksyms.c
> to let this module work again.
Recent SYMBIOS chips (810a, 825a, 875) are able to use PCI
READ MULTIPLE and PCI WRITE AND INVALIDE commands.
These commands are recommended by PCI local bus specs for
block transfers accross the PCI bus. They allow bursts on whole
cache lines.
However, this features require the PCI CACHE LINE SIZE to be properly
set in the PCI config space of SYMBIOS chips.
If it is not the case the chip will never use these PCI commands.
I've discovered recently that the PCI BIOS of my Tomcat I board just
sets PCI CACHE LINE SIZE to zero and does not set the PCI WRITE AND
INVALIDATE bit in the PCI COMMAND register.
Some other Mother Boards with same chipset (triton HX) seems to use
a PCI BIOS that sets properly the PCI CACHE LINE register but not
the PCI WRITE AND INVALIDATE feature.
I use my system with these PCI features properly set in the config
space of my 810a and 875 since severall weeks and I did not
have had any problem.
Indeed, it is normally not the role of a driver to set these registers.
Allowing chips to use enhanced PCI commands may cause problems with
bad designed hardware. The BIOS author probably wanted to avoid such
situations and so chose some very safe setup I am not going to ever
accept to use. Doing that, he just disallows new SYMBIOS chips to use
the normal PCI commands that are recommended by the PCI 2.1 specs and
that seems to work ok on my system.
I am not sure the code that hacks the PCI CACHE LINE SIZE and the
PCI WRITE AND INVALIDATE bit works in all situation.
I just assume cache line size=8 for Pentium class processors and 4 for
486 class processors.
In order to fix the compilation problem, just change:
#ifdef __i386
to
#if defined(__i386) && !defined(MODULE)
in the ncr53c8xx.c driver file.
The option that fix-up the PCI config space (if necessary) in order to
allow new 53C8XX chips to use recommended optimized PCI commands can
only be enabled from the boot command line (ncr53c8xx=pcifix:3),
(unless you hack the driver in order it does do this fix-up by default)
Gerard.