> > P.P.S If i compile as SMP, it barfs in calibrate_APIC_clock on my Cyrix 6x86
> > P166+ (if necessary, I will repeat the experiment and hand transcribe
> > the Oops). Yes I know that Cyrix 6x86s are not exactly smp-capable, just
> > wondering if a more graceful fallback is possible or desirable.
>
> We could check the APIC present CPUID bit assuming the Cyrix 6x86 gets that
> right
It does. However the AMD K5 Model 0 has two flags swapped and I think
(from memory) that they are APIC and PGE (9 and 13). The next "Cyrix"
patch will swap them back (as long as you read x86_flags and don't
do your own CPUID). I have no idea of global pages actually work
on the model 0 K5 though... :-)
Mike
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