Re: [PATCH] NMI trap revised (was Re: NMI errors in 2.0.30??)

Martin Mares (
Fri, 9 May 1997 16:11:57 +0200


> Are you sure? My references either say bits 2 and 3 must be set to enable bits 6
> and 7 or the references are silent. None say that bits 6 and 7 are always valid.

I'm not absolutely sure as different specs contradict each other. For example,
Intel Triton PIIX datasheets clearly say these bits are always valid, on the other
hand Tech Help and several DOS port description guides define these bits as
XT keyboard disable. AMD-640 chipset specs don't mention this port at all
and OPTI Vendetta chipset specs state the same as Intel. => It seems bits 6 and 7
are always valid on modern MB's, but maybe not on the old ones.

> > The kernel should _not_ enable these bits as it would break lots of systems
> > having non-parity memory.
> How?

This would probably enable the parity checks there causing approx. half of all
memory accesses to cause NMI.

Conclusion: We should not enable these bits explicitly and we should honor
the information in bits 6 and 7 only if the corresponding NMI sources are set
in bits 2 and 3 (they are hopefully readable on all MB's since the XT).