Re: Cyrix M2

Mike Jagdis (
Thu, 24 Apr 1997 10:38:01 +0100 (GMT/BST)

On Wed, 23 Apr 1997, Thayne Harbaugh wrote:

> I remember a big discussion about MMX that happened not
> too long ago. The conclusion was that the penalty to switch
> between FP & MMX was too great for a true multitasking OS.
> So now Cyrix has their new M2 (yet to be seen) that has L1 cache
> access as fast as the registers as well as L1 cache locking and
> a few other neat features. Does this have the same performance
> hit for switching as the Pentium or is it faster?

It has the same hit as saving and restoring the FP registers
at least. Whether that hit is the same on Cyrix and Intel
is not clear. Things like write behind and write gathering in
the L1 and L2 caches could cause differences. But you are talking
about pretty close order I guess :-).

(Cyrix had to use FP registers for MMX to be at all compatible
with Intel. I don't think they liked having to do it :-). Intel
did it to save the cost of engineering their silicon to hold a
few more registers.)


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