Re: 2.0.x Cyrix patch on 2.0.30

Alan Cox (
Fri, 18 Apr 1997 19:16:51 +0100 (BST)

> of locking down an L1 cache line. Anyone care to speculate how that
> could benefit us? Cyrix suggest that since L1 accesses are as fast
> as register accesses you could use it to implement large register
> files. We've all complained about how few general purpose registers
> x86 chips have...

Having L1 cache at register speed really requires someone totally rewrites
the x86 machine description for the Cyrix to do cache line allocation for
automatic variables and cache line scheduling on variables.

Big job but might be quite a win