> Dunno about AMD cache sizes.
Have a look at http://www.amd.com/html/products/pcd/mpf/pres1.html and
follow the arrows. The main features are:
Cache are 32kB each (I and D), but only 2-way set associative.
Instruction fetcher performs predecoding and stores the additional
information along with the instructions in I-cache.
Floating point multiply takes only 2 cycles (5 on PPro).
Floating point add takes 2 cycles (3 on PPro).
Much lower branch misprediction penalty than PPro.
Fits into a Pentium socket.
But I don't have any to check their claims. Anyway it looks good even after
removing marketing hype.
Gabriel