Re: Triton chipset & bridge optimizing

Gerard Roudier (groudier@iplus.fr)
Wed, 20 Mar 1996 00:59:49 +0000 (GMT)


On Tue, 19 Mar 1996, Graham Mitchell wrote:

Graham,

I dont know the effect of all those parameters.
On the other hand, I will not take the risk to be too wrong.
Here is what I can tell about your chipset configuration:

> CPU: Pentium, 60MHz, CPU->Memory posting ON, read around write
OK

> Warning: Cache parity disabled!
You L2 cache does not include a parity bit. It is harmless.

> Cache: 256KB writeback, cache clocks=3-2-2-2/4-2-2-2
20ns L2 cache probably.

> Cache flags: cache-all byte-control
OK

> DRAM: memory clocks=X-4-4-4 (70ns)
With a external BUS of 60 MHZ, X-4-4-4 / X-3-3-3 should work with 70 ns RAMS.
X-3-3-3 / X-3-3-3 should work with 60 ns RAMS.

> CPU->PCI: posting ON, burst mode ON, PCI clocks=2-1-1-1
OK

> PCI->Memory: posting ON
OK

> Refresh: RAS#Only BurstOf4

I think that except perhaps the memory timing, all is OK and fully optimized
for your chipset.

> Looks like the writeback cache is on from this.
It is quite sure.

> however this seems at
> variance with dmesg info about L2 cache not being supported.
"L2 cache not supported" means that OPTIMIZATION of the L2 cache is not
supported and does not mean at all that the L2 cache is not optimized.

> Does 23.96 bogomips seem the right ballpark for a 60MHz Pentium.....?
It is OK.
With a P90 we get about 36.05 Bogomips.
There are lots of papers about Bogomips that you can find on CDs or at some
famous FTP servers.

Regards, Gerard.