Re: [PATCH 1/2] arm64: dts: imx8mp: Add DT nodes for the two ISPs

[Adam Ford]

On Mon, Mar 25, 2024 at 10:14 AM Laurent Pinchart
<laurent.pinchart@xxxxxxxxxxxxxxxx> wrote:
>
> Hi Adam,
>
> On Wed, Mar 20, 2024 at 07:35:46AM -0500, Adam Ford wrote:
> > On Wed, Nov 29, 2023 at 3:31 AM Paul Elder wrote:
> > >
> > > The ISP supports both CSI and parallel interfaces, where port 0
> > > corresponds to the former and port 1 corresponds to the latter. Since
> > > the i.MX8MP's ISPs are connected by the parallel interface to the CSI
> > > receiver, set them both to port 1.
> > >
> > > Signed-off-by: Paul Elder <paul.elder@xxxxxxxxxxxxxxxx>
> >
> > Paul, are you able to resend this now that the driver part has been
> > merged into the main branch?
> >
> > If you can't, I can resend it on your behalf.
>
> I've just sent a v2, you're on CC.

Thanks!

adam
>
> > > ---
> > >  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 50 +++++++++++++++++++++++
> > >  1 file changed, 50 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > index c9a610ba4836..25579d4c58f2 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > @@ -1604,6 +1604,56 @@ isi_in_1: endpoint {
> > >                                 };
> > >                         };
> > >
> > > +                       isp_0: isp@32e10000 {
> > > +                               compatible = "fsl,imx8mp-isp";
> > > +                               reg = <0x32e10000 0x10000>;
> > > +                               interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> > > +                               clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
> > > +                                        <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> > > +                                        <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> > > +                               clock-names = "isp", "aclk", "hclk";
> > > +                               assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>;
> > > +                               assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> > > +                               assigned-clock-rates = <500000000>;
> > > +                               power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
> > > +                               fsl,blk-ctrl = <&media_blk_ctrl 0>;
> > > +                               status = "disabled";
> > > +
> > > +                               ports {
> > > +                                       #address-cells = <1>;
> > > +                                       #size-cells = <0>;
> > > +
> > > +                                       port@1 {
> > > +                                               reg = <1>;
> > > +                                       };
> > > +                               };
> > > +                       };
> > > +
> > > +                       isp_1: isp@32e20000 {
> > > +                               compatible = "fsl,imx8mp-isp";
> > > +                               reg = <0x32e20000 0x10000>;
> > > +                               interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> > > +                               clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
> > > +                                        <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> > > +                                        <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> > > +                               clock-names = "isp", "aclk", "hclk";
> > > +                               assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>;
> > > +                               assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> > > +                               assigned-clock-rates = <500000000>;
> > > +                               power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
> > > +                               fsl,blk-ctrl = <&media_blk_ctrl 1>;
> > > +                               status = "disabled";
> > > +
> > > +                               ports {
> > > +                                       #address-cells = <1>;
> > > +                                       #size-cells = <0>;
> > > +
> > > +                                       port@1 {
> > > +                                               reg = <1>;
> > > +                                       };
> > > +                               };
> > > +                       };
> > > +
> > >                         dewarp: dwe@32e30000 {
> > >                                 compatible = "nxp,imx8mp-dw100";
> > >                                 reg = <0x32e30000 0x10000>;
>
> --
> Regards,
>
> Laurent Pinchart