Re: [PATCH bpf-next 1/2] bpf: Add arm64 JIT support for PROBE_MEM32 pseudo instructions.

[Kumar Kartikeya Dwivedi]

On Thu, 14 Mar 2024 at 16:00, Puranjay Mohan <puranjay12@xxxxxxxxx> wrote:
>
> Add support for [LDX | STX | ST], PROBE_MEM32, [B | H | W | DW]
> instructions.  They are similar to PROBE_MEM instructions with the
> following differences:
> - PROBE_MEM32 supports store.
> - PROBE_MEM32 relies on the verifier to clear upper 32-bit of the
>   src/dst register
> - PROBE_MEM32 adds 64-bit kern_vm_start address (which is stored in R28
>   in the prologue). Due to bpf_arena constructions such R28 + reg +
>   off16 access is guaranteed to be within arena virtual range, so no
>   address check at run-time.
> - PROBE_MEM32 allows STX and ST. If they fault the store is a nop. When
>   LDX faults the destination register is zeroed.
>
> To support these on arm64, we do tmp2 = R28 + src/dst reg and then use
> tmp2 as the new src/dst register. This allows us to reuse most of the
> code for normal [LDX | STX | ST].
>
> Signed-off-by: Puranjay Mohan <puranjay12@xxxxxxxxx>
> ---

Hi Alexei,
Puranjay and I were discussing this stuff off list and noticed that
atomic instructions are not handled.
It turns out that will cause a kernel crash right now because the
32-bit offset into arena will be dereferenced directly.

e.g. something like this:

@@ -55,6 +56,7 @@ int arena_list_add(void *ctx)
                test_val++;
                n->value = i;
                arena_sum += i;
+               __sync_fetch_and_add(&arena_sum, 0);
                list_add_head(&n->node, list_head);
        }
 #else

I will try to prepare a fix for the x86 JIT. Puranjay will do the same
for his set.