RE: [PATCH 0/1] Add XSAVE layout description to Core files for debuggers to support varying XSAVE layouts

[Willgerodt, Felix]

> -----Original Message-----
> From: Vignesh Balasubramanian <vigbalas@xxxxxxx>
> Sent: Donnerstag, 14. März 2024 12:23
> To: linux-kernel@xxxxxxxxxxxxxxx; linux-toolchains@xxxxxxxxxxxxxxx
> Cc: mpe@xxxxxxxxxxxxxx; npiggin@xxxxxxxxx; christophe.leroy@xxxxxxxxxx;
> aneesh.kumar@xxxxxxxxxx; naveen.n.rao@xxxxxxxxxxxxx;
> ebiederm@xxxxxxxxxxxx; keescook@xxxxxxxxxxxx; x86@xxxxxxxxxx; linuxppc-
> dev@xxxxxxxxxxxxxxxx; linux-mm@xxxxxxxxx; bpetkov@xxxxxxx;
> jinisusan.george@xxxxxxx; matz@xxxxxxx; binutils@xxxxxxxxxxxxxx;
> jhb@xxxxxxxxxxx; Willgerodt, Felix <felix.willgerodt@xxxxxxxxx>; Vignesh
> Balasubramanian <vigbalas@xxxxxxx>
> Subject: [PATCH 0/1] Add XSAVE layout description to Core files for debuggers to
> support varying XSAVE layouts
> 
> This patch proposes to add an extra .note section in the corefile to dump the
> CPUID information of a machine. This is being done to solve the issue of tools like
> the debuggers having to deal with coredumps from machines with varying XSAVE
> layouts in spite of having the same XCR0 bits. The new proposed .note section, at
> this point, consists of an array of records containing the information of each
> extended feature that is present. This provides details about the offsets and the
> sizes of the various extended save state components of the machine where the
> application crash occurred. Requesting a review for this patch.
> 
> Some background:
> 
> The XSAVE layouts of modern AMD and Intel CPUs differ, especially since Memory
> Protection Keys and the AVX-512 features have been inculcated into the AMD
> CPUs. This is since AMD never adopted (and hence never left room in the XSAVE
> layout for) the Intel MPX feature. Tools like GDB had assumed a fixed XSAVE
> layout matching that of Intel (based on the XCR0 mask). 

Hi,

I am a GDB developer and very much in favour of getting rid of the 
interim solution added to GDB. It doesn't scale well, as soon as we add new state
that has the same size as some existing state.

I am wondering if it wouldn't be easier for everyone if corefiles would just
contain space for all possible XSAVE components? Regardless of whether the CPU
supports it or whether or not AMD or Intel ever supported the feature.
Or if we would at least not drop some state from the middle, like in this case.

Regards,
Felix
Intel Deutschland GmbH
Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de <http://www.intel.de>
Managing Directors: Christin Eisenschmid, Sharon Heck, Tiffany Doon Silva  
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928