[PATCH v2 07/10] clk: renesas: r9a08g045: Add support for power domains

From: Claudiu
Date: Thu Mar 07 2024 - 09:09:53 EST


From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>

Instantiate power domains for the currently enabled IPs of R9A08G045 SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
---

Change in v2:
- used DEF_REG_CONF() to describe register offests and bits
- updated MSTOP bitmask for ddr domain
- updated MSTOP config for oftde_ddr
- kept the same description for gic as the CPG_BUS_ACPU_MSTOP register
documentation in the latest HW manual version is wrong and it will be
fixed; proper description for GIC is located in "Registers for Module
Standby Mode" table
- haven't added watchdog domain (was missing in v1, too, by mistake) as
the watchdog restart handler will fail w/o patch [1]; with this pm domain
support the watchdog will fail to probe; not sure what is the best
option until [1] will be integrated

[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20240228083253.2640997-10-claudiu.beznea.uj@xxxxxxxxxxxxxx

drivers/clk/renesas/r9a08g045-cpg.c | 61 +++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)

diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index c3e6da2de197..c64769082f5b 100644
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -240,6 +240,62 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
};

+static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
+ /* Keep always-on domain on the first position for proper domains registration. */
+ DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON,
+ DEF_REG_CONF(0, 0),
+ DEF_REG_CONF(0, 0),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("gic", R9A08G045_PD_GIC,
+ DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)),
+ DEF_REG_CONF(CPG_PWRDN_IP1, BIT(2)),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("ia55", R9A08G045_PD_IA55,
+ DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)),
+ DEF_REG_CONF(CPG_PWRDN_IP1, BIT(3)),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("dmac", R9A08G045_PD_DMAC,
+ DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)),
+ DEF_REG_CONF(0, 0),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("ddr", R9A08G045_PD_DDR,
+ DEF_REG_CONF(CPG_BUS_PERI_DDR_MSTOP, GENMASK(1, 0)),
+ DEF_REG_CONF(CPG_PWRDN_IP2, BIT(0)),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("tzcddr", R9A08G045_PD_TZCDDR,
+ DEF_REG_CONF(CPG_BUS_TZCDDR_MSTOP, GENMASK(2, 0)),
+ DEF_REG_CONF(CPG_PWRDN_IP2, BIT(1)),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("otfde_ddr", R9A08G045_PD_OTFDE_DDR,
+ DEF_REG_CONF(CPG_BUS_PERI_CPU2_MSTOP, BIT(2)),
+ DEF_REG_CONF(CPG_PWRDN_IP2, BIT(2)),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("sdhi0", R9A08G045_PD_SDHI0,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)),
+ DEF_REG_CONF(CPG_PWRDN_IP1, BIT(13)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("sdhi1", R9A08G045_PD_SDHI1,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)),
+ DEF_REG_CONF(CPG_PWRDN_IP1, BIT(14)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("sdhi2", R9A08G045_PD_SDHI2,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)),
+ DEF_REG_CONF(CPG_PWRDN_IP1, BIT(15)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("eth0", R9A08G045_PD_ETHER0,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)),
+ DEF_REG_CONF(CPG_PWRDN_IP1, BIT(11)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("eth1", R9A08G045_PD_ETHER1,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)),
+ DEF_REG_CONF(CPG_PWRDN_IP1, BIT(12)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("scif0", R9A08G045_PD_SCIF0,
+ DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),
+ DEF_REG_CONF(0, 0),
+ RZG2L_PD_F_NONE),
+};
+
const struct rzg2l_cpg_info r9a08g045_cpg_info = {
/* Core Clocks */
.core_clks = r9a08g045_core_clks,
@@ -260,5 +316,10 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = {
.resets = r9a08g045_resets,
.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */

+ /* Power domains */
+ .pm_domains = r9a08g045_pm_domains,
+ .num_pm_domains = ARRAY_SIZE(r9a08g045_pm_domains),
+ .pm_domain_pwrdn_mstop = true,
+
.has_clk_mon_regs = true,
};
--
2.39.2