Re: [PATCH 2/4] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells

[Krzysztof Kozlowski]

On 05/03/2024 12:17, Markus Schneider-Pargmann wrote:
> Hi Krzysztof,
> 
> On Tue, Mar 05, 2024 at 08:43:03AM +0100, Krzysztof Kozlowski wrote:
>> On 04/03/2024 11:36, Markus Schneider-Pargmann wrote:
>>> Hi,
>>>
>>> On Sat, Feb 17, 2024 at 03:25:30PM +0100, Krzysztof Kozlowski wrote:
>>>> On 14/02/2024 10:31, Markus Schneider-Pargmann wrote:
>>>>> Hi Rob,
>>>>>
>>>>> On Tue, Feb 06, 2024 at 06:43:05PM +0000, Rob Herring wrote:
>>>>>> On Tue, Feb 06, 2024 at 03:37:09PM +0100, Markus Schneider-Pargmann wrote:
>>>>>>> The information k3-socinfo requires is stored in an efuse area. This
>>>>>>> area is required by other devices/drivers as well, so using nvmem-cells
>>>>>>> can be a cleaner way to describe which information are used.
>>>>>>>
>>>>>>> If nvmem-cells are supplied, the address range is not required.
>>>>>>> Cells chipvariant, chippartno and chipmanufacturer are introduced to
>>>>>>> cover all required information.
>>>>>>>
>>>>>>> Signed-off-by: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx>
>>>>>>> Reviewed-by: Andrew Davis <afd@xxxxxx>
>>>>>>> ---
>>>>>>>  .../bindings/hwinfo/ti,k3-socinfo.yaml        | 23 ++++++++++++++++++-
>>>>>>>  1 file changed, 22 insertions(+), 1 deletion(-)
>>>>>>>
>>>>>>> diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>>>>>> index dada28b47ea0..f085b7275b7d 100644
>>>>>>> --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>>>>>> +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>>>>>> @@ -26,9 +26,24 @@ properties:
>>>>>>>    reg:
>>>>>>>      maxItems: 1
>>>>>>>  
>>>>>>> +  nvmem-cells:
>>>>>>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>>>>>>> +
>>>>>>> +  nvmem-cell-names:
>>>>>>> +    items:
>>>>>>> +      - const: chipvariant
>>>>>>> +      - const: chippartno
>>>>>>> +      - const: chipmanufacturer
>>>>>>> +
>>>>>>>  required:
>>>>>>>    - compatible
>>>>>>> -  - reg
>>>>>>> +
>>>>>>> +oneOf:
>>>>>>> +  - required:
>>>>>>> +      - reg
>>>>>>> +  - required:
>>>>>>> +      - nvmem-cells
>>>>>>> +      - nvmem-cell-names
>>>>>>>  
>>>>>>>  additionalProperties: false
>>>>>>>  
>>>>>>> @@ -38,3 +53,9 @@ examples:
>>>>>>>          compatible = "ti,am654-chipid";
>>>>>>>          reg = <0x43000014 0x4>;
>>>>>>>      };
>>>>>>> +  - |
>>>>>>> +    chipid: chipid@14 {
>>>>>>> +        compatible = "ti,am654-chipid";
>>>>>>
>>>>>> This isn't compatible if you have a completely different way to access 
>>>>>> it. 
>>>>>
>>>>> Thanks, it is not entirely clear to me how I could go forward with this?
>>>>> Are you suggesting to use a different compatible? Or is it something
>>>>> else I could do to proceed with this conversion?
>>>>
>>>> What you claim now, is that you have one device with entirely different
>>>> interfaces and programming model. So either this is not the same device
>>>> or you just wrote bindings to whatever you have in driver.
>>>>
>>>> Nothing in commit msg explains this.
>>>>
>>>> What you should do? Depends. If you just write bindings for driver, then
>>>> stop. It's a NAK. Instead write bindings for hardware.
>>>>
>>>> If the first choice, just the hardware is somehow like this, then
>>>> explain in commit msg and device description, how this device can be
>>>> connected over other bus, not MMIO. You can draw some schematics in
>>>> commit msg explaining architecture etc.
>>>
>>> Sorry the information provided in the commit message is not very clear.
>>>
>>> The basic access to the registes is still MMIO. nvmem is used to have a
>>> better abstraction and cleaner description of the hardware.
>>>
>>> Currently most of the data is exported using the parent syscon device.
>>> The relevant data is read-only and contained in a single register with
>>> offset 0x14:
>>>   - Chip variant
>>>   - Chip part number
>>>   - Chip manufacturer
>>>
>>> There are more read-only registers in this section of address space.
>>> These are relevant to other components as they define the operating
>>> points for example. For the OPP table relevant are chip variant and chip
>>> speed (which is in a different register).
>>>
>>> Instead of devices refering to this whole register range of 0x20000 in
>>
>> Whaaaaat?
>>
>>> size, I would like to introduce this nvmem abstraction in between that
>>> describes the information and can directly be referenced by the devices
>>> that depend on it. In this case the above mentioned register with offset
>>> 0x14 is instead described as nvmem-layout like this:
>>>
>>> 	nvmem-layout {
>>> 		compatible = "fixed-layout";
>>> 		#address-cells = <1>;
>>> 		#size-cells = <1>;
>>>
>>> 		chip_manufacturer: jtagidmfg@14 {
>>> 			reg = <0x14 0x2>;
>>> 			bits = <1 11>;
>>> 		};
>>>
>>> 		chip_partno: jtagidpartno@15 {
>>> 			reg = <0x15 0x3>;
>>> 			bits = <4 16>;
>>> 		};
>>>
>>> 		chip_variant: jtagidvariant@17 {
>>> 			reg = <0x17 0x1>;
>>> 			bits = <4 4>;
>>> 		};
>>>
>>> 		chip_speed: jtaguseridspeed@18 {
>>> 			reg = <0x18 0x4>;
>>> 			bits = <6 5>;
>>> 		};
>>>
>>> The underlying registers are still the same but they are not hidden
>>> by the syscon phandles anymore.
>>>
>>> The device that consumes this data would now use
>>>
>>> 	nvmem-cells = <&chip_variant>, <&chip_speed>;
>>> 	nvmem-cell-names = "chipvariant", "chipspeed";
>>>
>>> instead of
>>>
>>> 	syscon = <&wkup_conf>;
>>
>> syscon allows you this as well - via phandle arguments.
>>
>> nvmem is for non-volatile memory, like OCOTP and eFUSE. This is not for
>> accessing regular MMIO registers of system-controller, regardless
>> whether they are read-only or not (regmap handles this nicely, BTW).
>> Although probably Apple efuses and few others can confuse here. It still
>> looks like you convert regular system-controller block into nvmem,
>> because you prefer that Linux driver abstraction...
> 
> The above mentioned data is set in the factory. There is other
> non-volatile data, like device feature registers, in the same address
> region, as well as OTP data like MAC and USB IDs. But it is not a pure
> non-volatile memory region. The data is copied into these registers by
> the ROM at boot.

Still entire block is MMIO IP in your SoC, not a efuse/OTP hardware.
nvmem is not for regular MMIO registers which are sometimes R, sometimes RW.

Best regards,
Krzysztof