Re: [PATCH 6.7 000/163] 6.7.9-rc2 review

From: Ron Economos
Date: Tue Mar 05 2024 - 04:53:16 EST


On 3/5/24 1:48 AM, Ron Economos wrote:
On 3/5/24 1:27 AM, Ron Economos wrote:
On 3/5/24 12:31 AM, Conor Dooley wrote:
On Tue, Mar 05, 2024 at 07:58:57AM +0000, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 6.7.9 release.
There are 163 patches in this series, all will be posted as a response
to this one.  If anyone has any issues with these being applied, please
let me know.

Responses should be made by Thu, 07 Mar 2024 07:46:26 +0000.
Anything received after that time might be too late.
Samuel Holland <samuel.holland@xxxxxxxxxx>
     riscv: Save/restore envcfg CSR during CPU suspend

Samuel Holland <samuel.holland@xxxxxxxxxx>
     riscv: Add a custom ISA extension for the [ms]envcfg CSR
I left a comment in response to the off-list email about this patch,
I don't think it's gonna work as the number this custom extension has
been given exceeds the max in 6.7/

Cheers,
Conor.

Samuel Holland <samuel.holland@xxxxxxxxxx>
     riscv: Fix enabling cbo.zero when running in M-mode

Yeah, it doesn't work. Here's the new error:

arch/riscv/kernel/cpufeature.c:180:9: error: implicit declaration of function '__RISCV_ISA_EXT_SUPERSET'; did you mean 'RISCV_ISA_EXT_SVPBMT'? [-Werror=implicit-function-declaration]
  180 |         __RISCV_ISA_EXT_SUPERSET(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts),
      |         ^~~~~~~~~~~~~~~~~~~~~~~~
      |         RISCV_ISA_EXT_SVPBMT
arch/riscv/kernel/cpufeature.c:180:34: error: 'zicbom' undeclared here (not in a function)
  180 |         __RISCV_ISA_EXT_SUPERSET(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts),
      |                                  ^~~~~~
arch/riscv/kernel/cpufeature.c:181:34: error: 'zicboz' undeclared here (not in a function)
  181 |         __RISCV_ISA_EXT_SUPERSET(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts),
      |                                  ^~~~~~
cc1: some warnings being treated as errors
make[4]: *** [scripts/Makefile.build:243: arch/riscv/kernel/cpufeature.o] Error 1
make[3]: *** [scripts/Makefile.build:480: arch/riscv/kernel] Error 2
make[2]: *** [scripts/Makefile.build:480: arch/riscv] Error 2


This depends on a much earlier patch, "riscv: add ISA extension parsing for vector crypto" (upstream commit aec3353963b8de889c3f1ab7cc8ba11e99626606).

I think the best solution will be to revert all three patches.

riscv: Save/restore envcfg CSR during CPU suspend

riscv: Add a custom ISA extension for the [ms]envcfg CSR

riscv: Fix enabling cbo.zero when running in M-mode



Sorry, "riscv: Fix enabling cbo.zero when running in M-mode" is okay. Just the first two.