On Tue, Feb 20, 2024 at 04:14:36AM +0800, Yang Xiwen wrote:
On 2/20/2024 4:03 AM, Andrew Lunn wrote:There are a few MACs which require the PHY to provide a clock to the
I'm using generic PHY driver.Note it's unable to put the MDIO bus node outside of MAC controllerWhat PHY driver is being used? If there a specific PHY driver for this
(i.e. at the same level in the parent bus node). Because we need to
control all clocks and resets in FEMAC driver due to the phy reset
procedure. So the clocks can't be assigned to MDIO bus device, which is
an essential resource for the MDIO bus to work.
hardware? Does it implement soft reset?
It implements IEEE C22 standard. So there is a soft reset in BMCR register.
I'm wondering if you can skip hardware reset of the PHY and only do aThere must be someone to deassert the hardware reset control signal for the
software reset.
PHY. We can't rely on the boot loader to do that. And here even we choose to
skip the hardware reset procedure, the sequence of deasserting the reset
signals is also very important. (i.e. first PHY, then MAC and MACIF).
Opposite to the normal sequence. (we normally first register MAC driver, and
then PHY).
MAC before they can use their DMA engine. The PHY provides typically a
25MHz clock, which is used to driver the DMA. So long as you don't
touch the DMA, you can access other parts of the MAC before the PHY is
generating the clock.
So it might be possible to take the MAC and MACIF out of reset, then
create the MDIO bus, probe the PHY, take it out of reset so its
generating the clock, and then complete the rest of the MAC setup.
Andrew