[PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Add DT binding documentation for System Controller (SYS) found on
RZ/V2H{P} ("R9A09G057") SoC's.

SYS block contains the SYS_LSI_DEVID register which can be used to
retrieve SoC version information.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
---
Note, the reset index in example node will be update once the CPG
support is upstreamed.
---
 .../soc/renesas/renesas,r9a09g057-sys.yaml    | 59 +++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml

diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
new file mode 100644
index 000000000000..ba30d7734ee8
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/V2H{P} System Controller (SYS)
+
+maintainers:
+  - Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
+
+description:
+  The RZ/V2H{P} SYS (System Controller) controls the overall
+  configuration of the LSI and supports the following functions,
+  - Trust zone control
+  - Extend access by specific masters to address beyond 4GB space
+  - GBETH configuration
+  - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC/TSU
+  - LSI version
+  - WDT stop control
+  - General registers
+
+properties:
+  compatible:
+    const: renesas,r9a09g057-sys
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Clock from external oscillator
+
+  resets:
+    items:
+      - description: SYS_0_PRESETN reset signal
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+    extal_clk: extal-clk {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <24000000>;
+    };
+
+    sys: system-controller@10430000 {
+        compatible = "renesas,r9a09g057-sys";
+        reg = <0x10430000 0x10000>;
+        clocks = <&extal_clk>;
+        resets = <&cpg 1>;
+    };
-- 
2.34.1