[PATCH 12/16] clk: samsung: Pass mask to wait_until_mux_stable()

From: Sam Protsenko
Date: Fri Feb 16 2024 - 17:35:35 EST


Make it possible to use wait_until_mux_stable() for MUX registers where
the mask is different from MUX_MASK (e.g. in upcoming CPU clock
implementation for Exynos850).

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
---
drivers/clk/samsung/clk-cpu.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 744b609c222d..5ea618da0bc1 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -134,16 +134,16 @@ static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask)
* value was changed.
*/
static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
- unsigned long mux_value)
+ unsigned long mask, unsigned long mux_value)
{
unsigned long timeout = jiffies + msecs_to_jiffies(MAX_STAB_TIME);

do {
- if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
+ if (((readl(mux_reg) >> mux_pos) & mask) == mux_value)
return;
} while (time_before(jiffies, timeout));

- if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
+ if (((readl(mux_reg) >> mux_pos) & mask) == mux_value)
return;

pr_err("%s: re-parenting mux timed-out\n", __func__);
@@ -248,7 +248,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
/* select sclk_mpll as the alternate parent */
mux_reg = readl(base + regs->mux_sel);
writel(mux_reg | (1 << 16), base + regs->mux_sel);
- wait_until_mux_stable(base + regs->mux_stat, 16, 2);
+ wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 2);

/* alternate parent is active now. set the dividers */
writel(div0, base + regs->div_cpu0);
@@ -289,7 +289,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
/* select mout_apll as the alternate parent */
mux_reg = readl(base + regs->mux_sel);
writel(mux_reg & ~(1 << 16), base + regs->mux_sel);
- wait_until_mux_stable(base + regs->mux_stat, 16, 1);
+ wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 1);

if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);
@@ -361,7 +361,7 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
/* select the alternate parent */
mux_reg = readl(base + regs->mux_sel);
writel(mux_reg | 1, base + regs->mux_sel);
- wait_until_mux_stable(base + regs->mux_stat, 0, 2);
+ wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 2);

/* alternate parent is active now. set the dividers */
writel(div0, base + regs->div_cpu0);
@@ -389,7 +389,7 @@ static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
/* select apll as the alternate parent */
mux_reg = readl(base + regs->mux_sel);
writel(mux_reg & ~1, base + regs->mux_sel);
- wait_until_mux_stable(base + regs->mux_stat, 0, 1);
+ wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 1);

exynos_set_safe_div(cpuclk, div, div_mask);
spin_unlock_irqrestore(cpuclk->lock, flags);
--
2.39.2