Re: [PATCH v2 2/3] PCI: qcom: Read back PARF_LTSSM register

From: Bjorn Helgaas
Date: Wed Feb 14 2024 - 17:28:53 EST

On Wed, Feb 14, 2024 at 10:35:16PM +0100, Konrad Dybcio wrote:
> On 12.02.2024 22:17, Bjorn Helgaas wrote:
> > Maybe include the reason in the subject? "Read back" is literally
> > what the diff says.
> >
> > On Sat, Feb 10, 2024 at 06:10:06PM +0100, Konrad Dybcio wrote:
> >> To ensure write completion, read the PARF_LTSSM register after setting
> >> the LTSSM enable bit before polling for "link up".
> >
> > The write will obviously complete *some* time; I assume the point is
> > that it's important for it to complete before some other event, and it
> > would be nice to know why that's important.
> Right, that's very much meaningful on non-total-store-ordering
> architectures, like arm64, where the CPU receives a store instruction,
> but that does not necessarily impact the memory/MMIO state immediately.

I was hinting that maybe we could say what the other event is, or what
problem this solves? E.g., maybe it's as simple as "there's no point
in polling for link up until after the PARF_LTSSM store completes."

But while the read of PARF_LTSSM might reduce the number of "is the
link up" polls, it probably wouldn't speed anything up otherwise, so I
suspect there's an actual functional reason for this patch, and that's
what I'm getting at.