Re: [PATCH v2 0/7] Add tuning algorithm for delay chain

From: Judith Mendez
Date: Mon Feb 12 2024 - 12:59:48 EST

Hi Francesco,

On 2/12/24 11:32 AM, Francesco Dolcini wrote:
Hi Judith,

On Mon, Feb 12, 2024 at 10:33:35AM -0600, Judith Mendez wrote:
Hi Francesco,

On 2/11/24 10:02 AM, Francesco Dolcini wrote:
On Tue, Feb 06, 2024 at 07:15:13PM -0600, Judith Mendez wrote:
This patch series introduces a new tuning algorithm for
mmc. The new algorithm should be used when delay chain is
enabled. The ITAPDLY is selected from the largest passing
window and the buffer is not viewed as a circular buffer.
The new tuning algorithm is implemented as per the paper
published here [0] and has been tested on the following

Where is this `[0]`?

I must have missed linking the ref doc here, will add in next
iteration, thanks.

platforms: AM62x SK, AM62A SK, AM62p SK, AM64x SK, and AM64x

In the other patches you link some document, but I was not able to find
anything related to AM62, can you provide some reference on this
specific SOC?

This patch series fixes issues that affect all Sitara SoCs, not only
AM62x. However, I could use AM62x for reference, no problem.

I am really looking for documentation here that is related to the AM62
because I was not able to find anything and this is a topic of interest
for me.

The AM62x device datasheet:,
reference Table 7-79 for MMC0 and Table 7-97 for MMC1.

TRM, reference section 12.4.5 for MMCSD and section
Tuning Sequence that we currently implement in the sdhci_am654 driver.
Section for MMCSD registers, SS_CFG_PHY_CTRL_1,
SS_CFG_PHY_CTRL_5, and SS_CFG_PHY_CTRL_5 are usually of higher interest.

Tuning algorithm, reference: which is applicable for AM62x, DLL is not applicable
for AM62x, so the tuning algorithm should not consider the buffer
as a circular buffer.

~ Judith

Can you share something?