[PATCH 1/8] MIPS: Unify define of CP0 registers for uasm code

From: Jiaxun Yang
Date: Fri Feb 09 2024 - 13:08:48 EST

Definitions of uasm variant of CP0 registers are unified to
mipsregs.h, so they lay together with uasm variant of
the code.

Signed-off-by: Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx>
---
checkpatch warning:
"ERROR: Macros with complex values should be enclosed in parentheses"
is expected.
---
arch/mips/include/asm/mipsregs.h | 249 +++++++++++++++++++++++++++++++--------
arch/mips/kvm/entry.c | 27 +----
arch/mips/mm/tlbex.c | 18 +--
3 files changed, 200 insertions(+), 94 deletions(-)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index ec58cb76d076..59ea637c5975 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -42,59 +42,198 @@

/*
* Coprocessor 0 register names
+ *
+ * CP0_REGISTER variant is meant to be used in assembly code, C0_REGISTER
+ * variant is meant to be used in C (uasm) code.
*/
-#define CP0_INDEX $0
-#define CP0_RANDOM $1
-#define CP0_ENTRYLO0 $2
-#define CP0_ENTRYLO1 $3
-#define CP0_CONF $3
-#define CP0_GLOBALNUMBER $3, 1
-#define CP0_CONTEXT $4
-#define CP0_PAGEMASK $5
-#define CP0_PAGEGRAIN $5, 1
-#define CP0_SEGCTL0 $5, 2
-#define CP0_SEGCTL1 $5, 3
-#define CP0_SEGCTL2 $5, 4
-#define CP0_WIRED $6
-#define CP0_INFO $7
-#define CP0_HWRENA $7
-#define CP0_BADVADDR $8
-#define CP0_BADINSTR $8, 1
-#define CP0_COUNT $9
-#define CP0_ENTRYHI $10
-#define CP0_GUESTCTL1 $10, 4
-#define CP0_GUESTCTL2 $10, 5
-#define CP0_GUESTCTL3 $10, 6
-#define CP0_COMPARE $11
-#define CP0_GUESTCTL0EXT $11, 4
-#define CP0_STATUS $12
-#define CP0_GUESTCTL0 $12, 6
-#define CP0_GTOFFSET $12, 7
-#define CP0_CAUSE $13
-#define CP0_EPC $14
-#define CP0_PRID $15
-#define CP0_EBASE $15, 1
-#define CP0_CMGCRBASE $15, 3
-#define CP0_CONFIG $16
-#define CP0_CONFIG3 $16, 3
-#define CP0_CONFIG5 $16, 5
-#define CP0_CONFIG6 $16, 6
-#define CP0_LLADDR $17
-#define CP0_WATCHLO $18
-#define CP0_WATCHHI $19
-#define CP0_XCONTEXT $20
-#define CP0_FRAMEMASK $21
-#define CP0_DIAGNOSTIC $22
-#define CP0_DIAGNOSTIC1 $22, 1
-#define CP0_DEBUG $23
-#define CP0_DEPC $24
-#define CP0_PERFORMANCE $25
-#define CP0_ECC $26
-#define CP0_CACHEERR $27
-#define CP0_TAGLO $28
-#define CP0_TAGHI $29
-#define CP0_ERROREPC $30
-#define CP0_DESAVE $31
+#define CP0_INDEX $0
+#define C0_INDEX 0, 0
+
+#define CP0_RANDOM $1
+#define C0_RANDOM 1, 0
+
+#define CP0_ENTRYLO0 $2
+#define C0_ENTRYLO0 2, 0
+
+#define CP0_ENTRYLO1 $3
+#define C0_ENTRYLO1 3, 0
+
+#define CP0_CONF $3
+#define C0_CONF 3, 0
+
+#define CP0_GLOBALNUMBER $3, 1
+#define C0_GLOBALNUMBER 3, 1
+
+#define CP0_CONTEXT $4
+#define C0_CONTEXT 4, 0
+
+#define CP0_PAGEMASK $5
+#define C0_PAGEMASK 5, 0
+
+#define CP0_PAGEGRAIN $5, 1
+#define C0_PAGEGRAIN 5, 1
+
+#define CP0_SEGCTL0 $5, 2
+#define C0_SEGCTL0 5, 2
+
+#define CP0_SEGCTL1 $5, 3
+#define C0_SEGCTL1 5, 3
+
+#define CP0_SEGCTL2 $5, 4
+#define C0_SEGCTL2 5, 4
+
+#define CP0_PWBASE $5, 5
+#define C0_PWBASE 5, 5
+
+#define CP0_PWFIELD $5, 6
+#define C0_PWFIELD 5, 6
+
+#define CP0_PWCTL $5, 7
+#define C0_PWCTL 5, 7
+
+#define CP0_WIRED $6
+#define C0_WIRED 6, 0
+
+#define CP0_INFO $7
+#define C0_INFO 7, 0
+
+#define CP0_HWRENA $7
+#define C0_HWRENA 7, 0
+
+#define CP0_BADVADDR $8
+#define C0_BADVADDR 8, 0
+
+#define CP0_BADINSTR $8, 1
+#define C0_BADINSTR 8, 1
+
+#define CP0_BADINSTRP $8, 2
+#define C0_BADINSTRP 8, 2
+
+#define CP0_COUNT $9
+#define C0_COUNT 9, 0
+
+#define CP0_PGD $9, 7
+#define C0_PGD 9, 7
+
+#define CP0_ENTRYHI $10
+#define C0_ENTRYHI 10, 0
+
+#define CP0_GUESTCTL1 $10, 4
+#define C0_GUESTCTL1 10, 5
+
+#define CP0_GUESTCTL2 $10, 5
+#define C0_GUESTCTL2 10, 5
+
+#define CP0_GUESTCTL3 $10, 6
+#define C0_GUESTCTL3 10, 6
+
+#define CP0_COMPARE $11
+#define C0_COMPARE 11, 0
+
+#define CP0_GUESTCTL0EXT $11, 4
+#define C0_GUESTCTL0EXT 11, 4
+
+#define CP0_STATUS $12
+#define C0_STATUS 12, 0
+
+#define CP0_GUESTCTL0 $12, 6
+#define C0_GUESTCTL0 12, 6
+
+#define CP0_GTOFFSET $12, 7
+#define C0_GTOFFSET 12, 7
+
+#define CP0_CAUSE $13
+#define C0_CAUSE 13, 0
+
+#define CP0_EPC $14
+#define C0_EPC 14, 0
+
+#define CP0_PRID $15
+#define C0_PRID 15, 0
+
+#define CP0_EBASE $15, 1
+#define C0_EBASE 15, 1
+
+#define CP0_CMGCRBASE $15, 3
+#define C0_CMGCRBASE 15, 3
+
+#define CP0_CONFIG $16
+#define C0_CONFIG 16, 0
+
+#define CP0_CONFIG1 $16, 1
+#define C0_CONFIG1 16, 1
+
+#define CP0_CONFIG2 $16, 2
+#define C0_CONFIG2 16, 2
+
+#define CP0_CONFIG3 $16, 3
+#define C0_CONFIG3 16, 3
+
+#define CP0_CONFIG4 $16, 4
+#define C0_CONFIG4 16, 4
+
+#define CP0_CONFIG5 $16, 5
+#define C0_CONFIG5 16, 5
+
+#define CP0_CONFIG6 $16, 6
+#define C0_CONFIG6 16, 6
+
+#define CP0_LLADDR $17
+#define C0_LLADDR 17, 0
+
+#define CP0_WATCHLO $18
+#define C0_WATCHLO 18, 0
+
+#define CP0_WATCHHI $19
+#define C0_WATCHHI 19, 0
+
+#define CP0_XCONTEXT $20
+#define C0_XCONTEXT 20, 0
+
+#define CP0_FRAMEMASK $21
+#define C0_FRAMEMASK 21, 0
+
+#define CP0_DIAGNOSTIC $22
+#define C0_DIAGNOSTIC 22, 0
+
+#define CP0_DIAGNOSTIC1 $22, 1
+#define C0_DIAGNOSTIC1 22, 1
+
+#define CP0_DEBUG $23
+#define C0_DEBUG 23, 0
+
+#define CP0_DEPC $24
+#define C0_DEPC 24, 0
+
+#define CP0_PERFORMANCE $25
+#define C0_PERFORMANCE 25, 0
+
+#define CP0_ECC $26
+#define C0_ECC 26, 0
+
+#define CP0_CACHEERR $27
+#define C0_CACHEERR 27, 0
+
+#define CP0_TAGLO $28
+#define C0_TAGLO 28, 0
+
+#define CP0_DTAGLO $28, 2
+#define C0_DTAGLO 28, 2
+
+#define CP0_DDATALO $28, 3
+#define C0_DDATALO 28, 3
+
+#define CP0_STAGLO $28, 4
+#define C0_STAGLO 28, 4
+
+#define CP0_TAGHI $29
+#define C0_TAGHI 29, 0
+
+#define CP0_ERROREPC $30
+#define C0_ERROREPC 30, 0
+
+#define CP0_DESAVE $31
+#define C0_DESAVE 31, 0

/*
* R4640/R4650 cp0 register names. These registers are listed
@@ -291,6 +430,12 @@
#define ST0_DE 0x00010000
#define ST0_CE 0x00020000

+#ifdef CONFIG_64BIT
+#define ST0_KX_IF_64 ST0_KX
+#else
+#define ST0_KX_IF_64 0
+#endif
+
/*
* Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
* cacheops in userspace. This bit exists only on RM7000 and RM9000
diff --git a/arch/mips/kvm/entry.c b/arch/mips/kvm/entry.c
index aceed14aa1f7..96f64a95f51b 100644
--- a/arch/mips/kvm/entry.c
+++ b/arch/mips/kvm/entry.c
@@ -13,6 +13,7 @@

#include <linux/kvm_host.h>
#include <linux/log2.h>
+#include <asm/mipsregs.h>
#include <asm/mmu_context.h>
#include <asm/msa.h>
#include <asm/setup.h>
@@ -50,33 +51,9 @@
#define SP 29
#define RA 31

-/* Some CP0 registers */
-#define C0_PWBASE 5, 5
-#define C0_HWRENA 7, 0
-#define C0_BADVADDR 8, 0
-#define C0_BADINSTR 8, 1
-#define C0_BADINSTRP 8, 2
-#define C0_PGD 9, 7
-#define C0_ENTRYHI 10, 0
-#define C0_GUESTCTL1 10, 4
-#define C0_STATUS 12, 0
-#define C0_GUESTCTL0 12, 6
-#define C0_CAUSE 13, 0
-#define C0_EPC 14, 0
-#define C0_EBASE 15, 1
-#define C0_CONFIG5 16, 5
-#define C0_DDATA_LO 28, 3
-#define C0_ERROREPC 30, 0
-
#define CALLFRAME_SIZ 32

-#ifdef CONFIG_64BIT
-#define ST0_KX_IF_64 ST0_KX
-#else
-#define ST0_KX_IF_64 0
-#endif
-
-static unsigned int scratch_vcpu[2] = { C0_DDATA_LO };
+static unsigned int scratch_vcpu[2] = { C0_DDATALO };
static unsigned int scratch_tmp[2] = { C0_ERROREPC };

enum label_id {
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 4017fa0e2f68..c9d00d9cb3c8 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -32,6 +32,7 @@

#include <asm/cacheflush.h>
#include <asm/cpu-type.h>
+#include <asm/mipsregs.h>
#include <asm/mmu_context.h>
#include <asm/uasm.h>
#include <asm/setup.h>
@@ -280,23 +281,6 @@ static inline void dump_handler(const char *symbol, const void *start, const voi
#define K0 26
#define K1 27

-/* Some CP0 registers */
-#define C0_INDEX 0, 0
-#define C0_ENTRYLO0 2, 0
-#define C0_TCBIND 2, 2
-#define C0_ENTRYLO1 3, 0
-#define C0_CONTEXT 4, 0
-#define C0_PAGEMASK 5, 0
-#define C0_PWBASE 5, 5
-#define C0_PWFIELD 5, 6
-#define C0_PWSIZE 5, 7
-#define C0_PWCTL 6, 6
-#define C0_BADVADDR 8, 0
-#define C0_PGD 9, 7
-#define C0_ENTRYHI 10, 0
-#define C0_EPC 14, 0
-#define C0_XCONTEXT 20, 0
-
#ifdef CONFIG_64BIT
# define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
#else

--
2.43.0