Re: [PATCH v3] perf: CXL: fix mismatched cpmu event opcode

[Jonathan Cameron]

On Thu, 08 Feb 2024 10:34:15 +0900
Hojin Nam <hj96.nam@xxxxxxxxxxx> wrote:

> S2M NDR BI-ConflictAck opcode is described as 4 in the CXL
> r3.0 3.3.9 Table 3.43. However, it is defined as 3 in macro definition.
> 
> Fixes: 5d7107c72796 ("perf: CXL Performance Monitoring Unit driver")
> Signed-off-by: Hojin Nam <hj96.nam@xxxxxxxxxxx>

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>

Thanks,

Jonathan

> ---
> 
> Hi Jonathan,
> Sorry, I misunderstood your guide. 
> I roll-backed to v1 patch keeping fixes tag. Thank you!
> 
> Changes since v2:
> - Remove s2m_ndr_cmpm attribute and referecne added at v2 (Jonathan)
> 
> Changes since v1:
> - Add s2m_ndr_cmpm event attribute
> - Add fixes tag (Jonathan)
> 
> 
>  drivers/perf/cxl_pmu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c
> index 365d964b0f6a..bc0d414a6aff 100644
> --- a/drivers/perf/cxl_pmu.c
> +++ b/drivers/perf/cxl_pmu.c
> @@ -419,7 +419,7 @@ static struct attribute *cxl_pmu_event_attrs[] = {
>         CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmp,                     CXL_PMU_GID_S2M_NDR, BIT(0)),
>         CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmps,                    CXL_PMU_GID_S2M_NDR, BIT(1)),
>         CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmpe,                    CXL_PMU_GID_S2M_NDR, BIT(2)),
> -       CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_biconflictack,           CXL_PMU_GID_S2M_NDR, BIT(3)),
> +       CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_biconflictack,           CXL_PMU_GID_S2M_NDR, BIT(4)),
>         /* CXL rev 3.0 Table 3-46 S2M DRS opcodes */
>         CXL_PMU_EVENT_CXL_ATTR(s2m_drs_memdata,                 CXL_PMU_GID_S2M_DRS, BIT(0)),
>         CXL_PMU_EVENT_CXL_ATTR(s2m_drs_memdatanxm,              CXL_PMU_GID_S2M_DRS, BIT(1)),
> --
> 2.34.1